1. Field of the Disclosure
The present disclosure relates generally to integrated circuit (IC) design and more particularly to mitigation of stress migration in metallization structures of IC devices.
2. Description of the Related Art
Vacancies in the metallization structure of an integrated circuit (IC) device can be created under certain device fabrication conditions. Such vacancies tend to migrate over time, often as a result of changes in the thermal conditions, from regions of higher tensile stress (or lower compressive stress) to regions of lower tensile stress (or higher compressive stress) in the metallization structure in a process generally referred to as “stress migration” or “stress-induced voiding.” As vias tend to generate areas of lower tensile stress (or higher compressive stress) vacancies tend to migrate and agglomerate at vias over time, and thus impair the conductance of the vias. With the use of IC devices in high-temperature applications and the use of lower-k back-end-of-the-line (BEOL) dielectrics that have reduced ability to conduct and dissipate away heat and smaller metal geometries, stress migration has increasingly impacted IC device reliability.